Adc calibration

ABSTRACT

An analog to digital convertor (ADC) includes a plurality of comparators one of which is referred to as an auxiliary comparator (e.g., comparator “Aux”). This comparator Aux is calibrated in the background while other comparators function as usual. Once having been calibrated, the comparator Aux replaces a first comparator, which becomes a new comparator Aux, is calibrated, and replaces the second comparator. This second comparator becomes the new comparator Aux, is calibrated, and replaces the third comparator, etc., until all comparators are calibrated. In effect, at any one point in time, a comparator may be calibrated as desire while other comparators and thus the ADC are operating as usual.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of U.S. Provisional Patent Application Ser. No. 61/233,049 filed on Aug. 11, 2009 which is incorporated herein by reference in its entirety.

FIELD

This disclosure is generally related to ADCs (analog-to-digital converters). In various embodiments the ADC is calibrated in the background.

BACKGROUND

ADCs (analog-to-digital converters) frequently require calibration. An approach records the differential programmable current through a DAC to compensate for the comparator's output voltage offset at power-on. This recorded current value is then used to calibrate the comparator as needed. As time elapses, however, temperature and/or voltage variation can cause the threshold voltage of transistors in the ADC to change and the output voltage offset to drift, resulting in inaccurate calibration.

BRIEF DESCRIPTION OF THE DRAWINGS

The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the disclosure will be apparent from the description, drawings, and claims.

FIG. 1 shows an illustrative flash ADC upon which embodiments of the disclosure may be implemented.

FIG. 2 illustrates differential comparators being used in the ADC in FIG. 1, in accordance with an embodiment.

FIG. 3 shows a differential comparator of the flash ADC in FIG. 1 configured for calibration, in accordance with an embodiment.

FIG. 4 shows a flow chart illustrating a method embodiment for calibrating comparators of the ADC in FIG. 1.

Like reference symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION

Various embodiments, or examples, of the disclosure illustrated in the drawings are now being described using specific language. It will nevertheless be understood that no limitation of the scope of the invention is thereby intended. Any alterations and modifications in the described embodiments, and any further applications of principles of the disclosure described in this document are contemplated as would normally occur to one skilled in the art to which the disclosure relates. Reference numbers may be repeated throughout the embodiments, but this does not necessarily require that feature(s) of one embodiment apply to another embodiment, even if they share the same reference number.

FIG. 1 shows an exemplary flash ADC 100 upon which embodiments of the disclosure may be implemented. ADC 100 is an analog-to-digital converter commonly found in RF (radio frequency) communication applications. In general, if ADC 100 is an N-bit converter, then ADC 100 uses 2^(N)−1 comparators 130 to convert signals from analog to digital. Various embodiments of the disclosure use an extra comparator 130 for a total of 2^(N) comparators 130 such that at any point in time one comparator 130 may be calibrated while the other 2^(N)−1 comparators 130 continue to function as usual. In effect, each comparator 130 is in turn calibrated while the other 2^(N)−1 comparators 130 continue to function. For illustration purposes, ADC 100 is shown to be a 5-bit converter and thus uses 31 (2⁵−1) comparators 130. Various embodiments of the disclosure use an extra comparator 130 for a total of 32 (e.g., 2⁵) comparators 130 so that each comparator 130 may be in turn calibrated while the other 31 comparators 130 continue to function. Further, embodiments of the disclosure are explained in the context of a 5-bit converter, but are not limited, and applicable to N-bit converters.

Voltage Vref_P, voltage Vref_M, and the resistive divider comprising resistors R(1) to R(32) provide reference voltages Vref to each input of comparators 130. Those skilled in the art will recognize that the reference voltage Vref for each comparator 130 is one LSB (least significant bit) greater than the reference voltage for the next comparator. For example, the reference voltage Vref(1) for comparator 130(1) is one LSB greater than the reference voltage Vref(2) for comparator 130(2), and the reference voltage Vref(2) for comparator 130(2) is one LSB greater than the reference voltage Vref(3) for comparator 130(3), etc. In an embodiment, voltage Vref_P is at Vdd while Vref_M is at ground.

State machine 110 controls the order of calibration for each comparator 130, including generating signals SSWN and SSWP to activate and/or deactivate appropriate switches SWN and SWP for a comparator 130 to be calibrated or returned to normal operation. Depending on applications and design choices, comparators 130 may be calibrated in the sequence of the LSB comparator (e.g., comparator 130(1)) to the MSB comparator (e.g., comparator 130(31)) or in the sequence of the MSB comparator (e.g., comparator 130(31)) to the LSB comparator (e.g., comparator 130(1)). Alternatively, comparators 130 may be calibrated in any order as defined by the user. In the embodiment of FIG. 1, a comparator 130 is selected as an auxiliary comparator (e.g., comparator Aux), and comparators 130 are calibrated in the order from LSB to MSB. As a result, comparator Aux is first calibrated then replaces a first comparator, e.g., comparator 130(1), which becomes a new comparator Aux. This new comparator Aux is calibrated and replaces the next comparator, e.g., comparator 130(2), which becomes another new comparator Aux. This new comparator Aux is calibrated and replaces the next comparator, e.g., comparator 130(3), etc., until all comparators 130 are calibrated. During the calibration process, while comparator Aux is being calibrated the other 31 comparators 130 that are not under calibration continue to function. Depending on applications, state machine 110 may be implemented using hardware circuits including programmable logic devices or using a CPU (central processing unit) with software, and embodiments of the disclosure are not limited to any implementation method.

Signal Input serves as the normal positive input for comparators 130. Calibration signal CS serves to calibrate a comparator 130 under calibration (e.g., comparator Aux). In an embodiment signal CS including a differential signal of 0V is applied at the positive input of comparator Aux, and the output of comparator Aux is observed. If comparator Aux is un-calibrated, an offset value would appear at its output, which is then calibrated to zero volt. As a result, comparator Aux is calibrated.

A signal SSWN controls a corresponding switch SWN, which includes a left terminal TLN and a right terminal TRN. For example, when signal SSWN(1) is activated (e.g., high), it closes switch SSWN(1) to right terminal TRN, but when it is deactivated (e.g., low), it closes switch SSWN(1) to left terminal TLN. Switches SWN in conjunction with corresponding signals SSWN control the negative input of comparators 130. Either left terminal TLN or right terminal TRN of a switch SWN is to connect the negative input of a comparator 130 to its corresponding Vref. For example, as shown in FIG. 1, left terminal TLN of switch SWN(1) is connected to the negative input of comparator Aux while right terminal TRN of switch SWN(1) is connected to the negative input of comparator 130(1). A switch SWN connects the negative input of a comparator 130 then connected to the closed position of switch SWN to its corresponding Vref. For example, as shown in FIG. 1, switch SWN(1) being closed to right terminal TRN(1) connects the negative input of comparator 130(1) to its corresponding Vref(1); switch SWN(2) being closed to right terminal TRN(2) connects the negative input of comparator 130(2) to its Vref(2); and switch SWN(3) being closed to right terminal TRN(3) connects the negative input of comparator 130(3) to its corresponding Vref(3), etc. A comparator 130 having its negative input connected to Vref is under normal operation while a comparator 130 with its negative input not connected to Vref (e.g., connected to ground) is under calibration.

A signal SSWP controls a corresponding switch SWP, which includes a left terminal TLP and a right terminal TRP. For example, when signal SSWP(1) is activated (e.g., high), it closes switch SSWP(1) to right terminal TRP, but when it is deactivated (e.g., low), it closes switch SSWP(1) to left terminal TLP. Switches SWP in conjunction with corresponding signals SSWP control the positive input of comparators 130. The left terminal TLP of a switch SWP is to connect the positive input of a comparator 130 to calibration signal CS while the right terminal TRP of the same switch SWP is to connect the positive input of a comparator 130 to signal Input. For example, as shown in FIG. 1, left terminal TLP of switches SWP is connected to calibration signal CS while right terminal TRP of switches SWP is connected to signal Input. A switch SWP connects the positive input of a comparator 130 to either calibration signal CS or signal Input. For example, as shown in FIG. 1, switch SWP(1) being closed to right terminal TRP(1) connects the positive input of comparator Aux to signal Input; switch SWP(2) being closed to right terminal TRP(2) connects the positive input of comparator 130(1) to signal Input, switch SWP(3) being closed to right terminal TRP(3) connects the positive input of comparator 130(2) to signal Input, etc. A comparator 130 having its positive input connected to signal Input is under normal operation while a comparator 130 having its positive input connected to signal CS is under calibration.

Comparators 130 generate the digital code for ADC 100. For example, a comparator 130 produces a “1” when its analog input voltage is higher than the reference voltage applied to it (e.g., its Vref), and produces a “0” otherwise. As shown in FIG. 1, when switches SWN and SWP are appropriately closed the reference voltage Vref of comparators 130 is applied to their positive terminals. Various embodiments of the disclosure calibrate one comparator (e.g., comparator Aux) while the other 31 comparators 130 function as usual. Once comparator Aux has been calibrated various embodiments swap it with another comparator 130, which now becomes a new comparator Aux. Various embodiments then calibrate the new comparator Aux and after calibrating this new comparator Aux swap this new comparator Aux with another comparator 130 that has not been calibrated, etc., until all comparators 130 are calibrated. Swapping a comparator 130 for calibration and returning it to normal operation uses the corresponding switches SWN and SWP. In an embodiment, when a comparator 130 is calibrated its negative input is connected to ground while its positive input is connected to the calibration signal CS. Conversely, when a comparator 130 is in normal operation, its negative input is connected to its Vref and its positive input is connected to signal Input. Connecting the inputs of comparators 130 to appropriate signals (e.g., Vref, signal CS, signal Input, etc.) is done through switches SWN and SWP. Comparators 130 are shown as being single-ended wherein each terminal (e.g., a negative terminal and a positive terminal) includes a single terminal, but embodiments are not limited to single-ended comparators and are also applicable to other types of comparators including double-ended or differential comparators. For example, in a differential comparator, each of a negative terminal and a positive terminal includes two terminals, e.g., a negative and a positive terminal. Additional illustration regarding differential comparators is explained with respect to FIG. 2 below.

Frequency source Fs 140 in conjunction with clock signal CLK provides the clocks for various units including comparators 130, encoder 150, decimation filter 160, etc. In various embodiments, frequency source 140 provides different clocks to comparators 130 such that a comparator 130 under calibration can run at a frequency lower than a frequency used by comparators under normal operation.

Encoder 150 transforms thermometer code generated by comparators 130 to binary code. Those skilled in the art will recognize that the thermometer code is used to verify the region including the distribution of MSB (most significant bit) and LSB (least significant bit). Decimation filter 160 attenuates out of band signal to gain better performance for ADC 100.

FIG. 2 shows a comparator 200 illustrating a comparator 130(i), being in differential configuration, in accordance with an embodiment. Because of the differential configuration, output of comparator 200 includes a negative terminal Outn and a positive terminal Outp, and reference voltage Vref(i) for comparator 200 includes a positive polarity reference voltage Vrefp(i) and a negative polarity reference voltage Vrefn(i). A reference voltage Vrefp (e.g., reference voltage Vrefp(i)) is in fact a reference voltage having voltage Vref_P coupled to resistor R(1) and voltage Vref_M coupled to resistor R(32) as shown in FIG. 1. Voltage Vrefn is the inverse polarity of voltage Vrefp wherein voltage Vref_P is coupled to resistor R(32) and voltage Vref_M is coupled to resistor R(1). Further, the negative terminal of comparator 200 includes a negative terminal TNN and a positive terminal TNP. Similarly, the positive terminal includes a negative terminal TPN and a positive terminal TPP.

A switch SWN in FIG. 1 is shown in FIG. 2 including a switch SWNN and a switch SWNP to control corresponding terminals TNN and TNP. A switch SWNN includes a terminal TLNN and a terminal TRNN, either one of which is to connect a negative terminal TNN of a comparator 130 to its corresponding negative voltage reference Vrefn. A switch SWNP includes a terminal TLPN and a terminal TRPN, either of which is to connect a positive terminal TNP of a comparator 130 to its corresponding positive voltage reference Vrefp.

A switch SWP in FIG. 1 is shown in FIG. 2 as a switch SWPN and SWPP to control the corresponding terminals TPN and TPP. A switch SWPN includes a terminal TLPP and a terminal TRPP. A terminal TLPP is to connect terminal TPN of a comparator 130 to a negative polarity of calibration signal CS while a terminal TRPP is to connect terminal TPN of a comparator 130 to a negative polarity of signal Input. A switch SWPP includes a terminal TLPPP and a terminal TRPPP. A terminal TLPPP is to connect terminal TPP of a comparator 130 to a positive polarity of calibration signal CS while a terminal TRPPP is to connect terminal TPP of a comparator 130 to a positive polarity of signal Input.

Switches SWNN, SWNP, SWPN, and SWPP are controlled by appropriate signals generated and controlled by state machine 110. These signals, for simplicity, are not shown.

FIG. 3 shows comparator 200 with details and being configured for calibration in accordance with an embodiment using a circuit 310 known in the art. Transistors M1, M2, M3, M3′, M4, M4′, M7, and M9 form a pre-amplifier for comparator 200, and transistors M5, M6, and M8 form a latch circuit. Those skilled in the art will recognize that if comparator 200 is single-ended, transistors M3′ and M4′ and corresponding signals Vrp and Vrn would be excluded.

Calibration signals Vip, Vin, Vrp, and Vrn are coupled to terminals TNP, TNN, TPP, and TNP as shown.

Switches SWC(1) to SWC(16) serve to calibrate transistor 200. Each switch SWC can be closed to a left terminal TLC or a right terminal TRC. In the embodiment of FIG. 300, left terminals TLC are connected to signal Vrn and the source of transistor Mrn while right terminals TRC are connected to signal Vrp and the source of transistor Mrp. In an embodiment, all switches SWC are initially connected to left terminals TLC. As a result, signal Vrn is positive while signal Vrp is negative. Each switch SWC is then switched to right terminal TRC, and signal Vrn and/or Vrp is observed. When enough switches SWC are switched from left terminals TLC to right terminals TRC, the polarity of signals Vrn and Vrp change to negative and positive respectively. At that time, if comparator 200 is un-calibrated then the outputs Voutn and Voutp of comparator 200 shows a differential or offset voltage. Various embodiments of the disclosure use a voltage offset cancellation buffer to compensate for this voltage offset, e.g., allowing it to be zero volts. As a result, comparator 200 is calibrated. Additional calibration method using circuit 310 and the voltage offset cancellation buffer may be found at IEEE 2006 Custom Integrated Circuits Conference (CICC), entitled “A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS,” by Sunghyun Park et al.

FIG. 4 shows a flow chart 400 illustrating a method embodiment for calibrating comparators 130.

In block 410 a comparator 130, e.g., comparator Aux, is selected for calibration. In block 415 comparator Aux is configured for calibration including controlling appropriate switches SWN and SWP so that comparator Aux is not part of ADC 100 and ready for calibration while other comparators 130(1) to 130(31) continue to operate as normal. In the embodiment of FIG. 1, switch SWN(1) closes to right terminal TRN and switch SWP(1) closes to left terminal TRL while other switches SWN and SWP remain as shown in FIG. 1, resulting in a configuration where comparators 130(1) to 130(31) continue to function as normal.

In block 420, comparator Aux is calibrated. In an embodiment, the output offset of comparator Aux is determined using circuit 310, and this output offset is calibrated to be zero using the voltage offset canceling buffer, resulting in comparator Aux being calibrated. Other methods of calibrating comparator Aux may be used.

Once comparator Aux has been calibrated another comparator 130 is selected for calibration and is referred to as a “new” comparator Aux. In effect, the method 400 returns to block 410, and blocks 415 and 420 are performed with respect to the new comparator Aux. In an embodiment, the comparators Aux at blocks 410 are in the sequential order of the LSB comparator to the MSB comparator. That is, comparators 130 are calibrated in the order of 130(1), 130(2), . . . , to 130(31).

A number of embodiments of the disclosure have been described. It will nevertheless be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, there are various mechanisms to implement a switch (e.g., switch SWN, SWP, SWNN, SWNP, SWPN, SWPP, etc.), and embodiments of the disclosure are not limited to a particular method to implement a switch. Similarly, there are various mechanisms to implement a state machine (e.g., state machine 110), and embodiments of the disclosure are not limited to a particular way of implementing such a machine. The method embodiment in FIG. 4 uses a single-ended comparator for illustration, various embodiments of the disclosure are applicable to differential and other comparators. In such situations, appropriate switches SWNN, SWNP, SWPN and SWPP are configured for comparator Aux to be calibrated and returned to normal operation after calibration. The above method embodiment shows exemplary steps, but these steps are not necessarily required to be performed in the order shown. Steps may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of the invention. 

1. A method comprising: a) providing 2^(N) comparators in an N-bit analog-to-digital converter; the 2^(N) comparators being arranged from a least significant bit to a most significant bit; b) calibrating a one of the 2^(N) comparators while a remaining 2^(N)−1 comparators of the 2^(N) comparators are functioning in a normal operation of the analog-to-digital converter; c) substituting another one of the remaining 2^(N)−1 comparators with the calibrated comparator; and d) repeating steps b) and c) until the 2^(N) comparators are calibrated.
 2. The method of claim 1 wherein the 2^(N) comparators are calibrated in an order selected from a predefined order, an order from the least significant bit to the most significant bit, or an order from the most significant bit to the least significant bit.
 3. The method of claim 1 further including at least one switch at a negative terminal and at least one switch at a positive terminal of each of the 2 ^(N) comparators to configure each of the comparators for calibration and for normal operation.
 4. The method of claim 3 wherein each of the negative terminals is to receive a reference voltage or ground and the positive terminal is to receive a calibration signal or an input signal.
 5. The method of claim 1 further including at least one switch at at least one terminal of each of the 2^(N) comparators and injecting at least one signal to each comparator via the at least one respective switch.
 6. The method of claim 5 where the at least one signal includes one or a combination of ground, a calibration signal, a reference voltage, and an input signal for each of the 2^(N) comparators.
 7. The method of claim 1 wherein calibrating each of the 2^(N) comparators is done by injecting a calibration signal at a positive terminal of each of the 2^(N) comparators and grounding a negative terminal of each of the 2^(N) comparators.
 8. The method of claim 1 wherein calibrating each of the 2^(N) comparators is done at frequency lower than a frequency used by the remaining 2^(N)−1 comparators functioning in the normal operation of the analog-to-digital converter.
 9. A method comprising: providing a plurality of comparators for an analog-to-digital converter; providing a first pair of terminals and a second pair of terminals to each of the plurality of comparators; coupling the first pair of terminals to a corresponding first pair of switches and the second pair of terminals to a corresponding second pair of switches; using a respective first pair of switches and a respective second pair of switches to configure the corresponding comparator for calibration; calibrating the corresponding comparator; and using the respective first pair of switches and the respective second pair of switches to configure the corresponding comparator for normal operation; wherein while the corresponding comparator is being calibrated comparators other than the comparator being calibrated are operating as part of the analog-to-digital converter.
 10. The method of claim 9, wherein the analog-to-digital converter being an N-bit analog-to-digital converter and the plurality of comparators comprises 2^(N) comparators; and the comparators other than the comparator being calibrated include 2^(N)−1 comparators.
 11. The method of claim 9 wherein the plurality of comparators are calibrated in an order from a least significant bit to a most significant bit.
 12. The method of claim 9 wherein the plurality of comparators are calibrated in an order from a most significant bit to a least significant bit.
 13. The method of claim 9 wherein the respective first pair of switches are to connect a first pair of input signals to a respective first pair of terminals of the comparator and the respective second pair of switches are to connect a second pair of terminals of the corresponding comparator to a second pair of input signals or to a pair of calibration signals.
 14. The method of claim 9 wherein calibrating the comparator is done at a clock frequency lower than a clock frequency used at the normal operation of the analog-to-digital converter.
 15. A method comprising: providing 2^(N) comparators for an N-bit analog-to-digital converter; calibrating a one of the 2^(N) comparators while a remaining 2^(N)−1 comparators operate as part of the analog-to-digital converter; replacing a first comparator in the 2^(N)−1 comparators with the calibrated comparator; the calibrated comparator now operating as part of the analog-to-digital converter; calibrating the first comparator; replacing a second comparator in the 2 ^(N)−1 comparators with the calibrated first comparator; the calibrated first comparator now operating as part of the analog-to-digital converter; wherein the second comparator is a comparator next to a least significant bit comparator if the first comparator is the least significant bit comparator and the second comparator is a comparator next to a most significant bit comparator if the first comparator is the most significant bit comparator.
 16. The method of claim 15 wherein configuring switches connected to corresponding terminals of the first comparator replaces the first comparator and configuring switches connected to corresponding terminals of the second comparator replaces the second comparator.
 17. The method of claim 15 wherein a negative terminal of each of the 2^(N) the comparators receives a reference voltage or ground and a positive terminal of each of the 2^(N) comparators receives a calibration signal or an input signal.
 18. The method of claim 15 wherein calibrating each of the 2^(N) comparators is done by injecting a differential calibration signal at a respective positive terminal of the each of the 2^(N) comparators.
 19. The method of claim 18 wherein a respective negative terminal of each of the 2^(N) comparators.
 20. The method of claim 15 wherein calibrating each of the 2^(N) comparators is done at a frequency lower than a frequency used by the digital-to-analog converter in its normal operation. 